This invention is generally related to photodetecting semiconductor structures, and more specifically to photodiodes built using modern state of the art Complementary Metal Oxide Semiconductor (CMOS) fabrication processes.
A key component of all imaging systems is the photodetector, a device used to detect incident photons of visible light that originate from an object whose image is to be captured. Some prior art detection devices include those illustrated in FIGS. 1A and 1B. FIG. 1A illustrates a conventional technique for realizing a photodiode having a p-type doped substrate and a heavily doped N+ diffusion layer forming a p-n junction. The p-n junction is surrounded by an insulating oxide region. The N+ can be the source/drain diffusion of an adjacent transistor with the p-substrate being electrically contacted if necessary through conventional means.
Most photodiodes operate based on the principle of reverse-biasing a p-n junction diode such that a depletion region is formed. Next, the photodiode is subjected to incident light as shown which travels through the transparent oxide layers and into the silicon. The properties of the semiconductor are such that electron-hole pairs are generated both inside and outside the depletion region in response to the incident photons of visible light. These photogenerated electron-hole pairs are then swept away by diffusion and drift mechanisms and collected in the depletion region, thereby inducing a photocurrent representing a portion of the desired image.
A significant factor contributing to the sensitivity of a photodiode is its ability to capture as many incident photons as possible. In the example of FIG. 1A, virtually the entire N+ surface region above the depletion region is exposed, such that the incident photons can enter the structure through the large N+ region.
Integrated circuits built using modern and future generation fabrication processes are placing severe constraints on the design, implementation and performance of photodetecting structures. For example, modern integrated circuits such as image sensor ICs often attempt to incorporate a large number of photodetecting elements into the single IC die to meet limited physical space requirements. To meet such a challenge, the N+ region of the conventional photodiode in FIG. 1A must be made considerably smaller, thereby reducing the sensitivity of the photodiode structure.
Moreover, as the total power dissipated by an IC keeps increasing due to increasing complexity of the functions desired to be implemented, semiconductor fabrication processes keep up by allowing ever shrinking dimensions for the constituent circuit elements. Shrinking dimensions and larger numbers of interconnects, however, present increased resistances across the entire IC. For example, field effect transistor (FET) devices built using advanced CMOS processes have such small lateral and vertical dimensions that the resistance presented by the highly doped diffusion regions at the source and drain, as well as the polysilicon layer of the gate, become too high for effective signal transmission. To alleviate this problem, modern CMOS fabrication processes of the polysilicon self-aligned type provide the additional process step of covering the exposed silicon areas of the source, drain, and gate with a high conductivity material known as a silicide so as to present lower sheet resistance to the subsequently formed metal contacts. The silicide layer may be formed by applying a layer of metal such as titanium over the exposed silicon, and then causing a reaction between the titanium and silicon to transform the metal layer into a silicide.
In a self-aligned CMOS ("salicided") process, silicide strapping covers the entire N+ region of the source and drain in FIG. 1A. Because the silicide is virtually an opaque material, although up to 10% of light can get through at the thickness used in CMOS processes, the photodiode in FIG. 1A can rely only on incident photons which reach the depletion region from an angle. As a result, image arrays using photodiodes as in FIG. 1A are less effective in capturing an image when built on a CMOS salicided process.
One way to increase the number of photons that reach the p-n junction of FIG. 1A is to customize the silicide by adding process steps to further pattern the silicide, such that no silicide is formed over those regions used for photodetection. However, such an additional step will be time consuming and will increase manufacturing costs when the IC is mass produced.
Another way to increase the photon count appears in FIG. 1B as a series of "edge-intensive" photodiodes, where the incident light enters the photodiode through multiple translucent oxide regions surrounding an interdigitated silicide structure. Such a scheme renders a less effective photodiode as compared to the conventional non-salicided design in FIG. 1A as less photons are captured per unit area.
Finally, another disadvantage of the photodiode structures in FIGS. 1A and 1B is that they will require customized fabrication steps, especially with modern and future processes. That is because as transistor dimensions continue to shrink with advanced fabrication processes, the diffusion region depths for the source and drain of a field effect transistor (FET) must also shrink to permit the proper design of short channel FETs. As the diffusion depths shrink, the optical properties of photodiodes built using such diffusion-substrate junctions also change. Thus, to maintain the original optical properties, a different diffusion region will need to be built solely for photodiodes. This addition to the standard diffusion regions used for the FETs undesirably increases process complexity. Therefore, there is a need for a photodiode structure that can be implemented using standard IC fabrication processes but which also allows for flexibility in defining the optical properties.